Methods of Forming a Non-Volatile Resistive Oxide Memory Cell and Methods of Forming a Non-Volatile Resistive Oxide Memory Array

ABSTRACT

A method of forming a non-volatile resistive oxide memory cell includes forming a first conductive electrode of the memory cell as part of a substrate. Metal oxide-comprising material is formed over the first conductive electrode. Etch stop material is deposited over the metal oxide-comprising material. Conductive material is deposited over the etch stop material. A second conductive electrode of the memory cell which comprises the conductive material received is formed over the etch stop material. Such includes etching through the conductive material to stop relative to the etch stop material and forming the non-volatile resistive oxide memory cell to comprise the first and second conductive electrodes having both the metal oxide-comprising material and the etch stop material therebetween. Other implementations are contemplated.

RELATED PATENT DATA

This patent resulted from a divisional application of U.S. patent application Ser. No. 12/166,604 which was filed Jul. 2, 2008, and which is incorporated by reference herein.

TECHNICAL FIELD

Embodiments disclosed herein pertain to methods of forming a non-volatile resistive oxide memory cell and to methods of forming a non-volatile resistive oxide memory array.

BACKGROUND

Memory is one type of integrated circuitry, and is used in computer systems for storing data. Such is typically fabricated in one or more arrays of individual memory cells. The memory cells might be volatile, semi-volatile, or non-volatile. Non-volatile memory cells can store data for extended periods of time, and in many instances including when the computer is turned off. Volatile memory dissipates and therefore requires to be refreshed/rewritten, and in many instances including multiple times per second. Regardless, the smallest unit in each array is termed as a memory cell and is configured to retain or store memory in at least two different selectable states. In a binary system, the storage conditions are considered as either a “0” or a “1”. Further, some individual memory cells can be configured to store more than two levels of information.

Integrated circuitry fabrication continues to strive to produce smaller and denser integrated circuits. Accordingly, the fewer components an individual circuit device has, the smaller the construction of the finished device can be. Likely the smallest and simplest memory cell will be comprised of two conductive electrodes having a programmable material received there-between. Example materials include metal oxides which may or may not be homogenous, and may or may not contain other materials therewith. Regardless, the collective material received between the two electrodes is selected or designed to be configured in a selected one of at least two different resistive states to enable storing of information by an individual memory cell. When configured in one extreme of the resistive states, the material may have a high resistance to electrical current. In contrast in the other extreme, when configured in another resistive state, the material may have a low resistance to electrical current. Existing and yet-to-be developed memory cells might also be configured to have one or more additional possible stable resistive states in between a highest and a lowest resistance state. Regardless, the resistive state in which the programmable material is configured may be changed using electrical signals. For example, if the material is in a high-resistance state, the material may be configured to be in a low resistance state by applying a voltage across the material.

The programmed resistive state is designed to be persistent in non-volatile memory. For example, once configured in a resistive state, the material stays in such resistive state even if neither a current nor a voltage is applied to the material. Further, the configuration of the material may be repeatedly changed from one resistance state to another for programming the memory cell into different of at least two resistive states. Upon such programming, the resistive state of the material can be determined by appropriate signals applied to one or both of the two electrodes between which the material is received.

Certain metal oxides can be used as such materials in resistive memory cells. During fabrication, the materials which make up the memory elements are deposited and patterned to produce a desired finish shape and construction of the individual memory cells in an array of such cells. Accordingly, a conductive material is deposited for one of the electrodes, followed by deposition of at least some metal oxide for the programmable region, and followed by deposition of more conductive material for the other electrode of the memory cell. Often, the first and second conductive layers are fabricated as elongated conductive lines which run generally parallel an outermost major surface of the substrate upon which such are fabricated, yet generally orthogonal relative to one another.

Regardless, the three different regions of the memory cell are often patterned by etching using multiple masking and etching steps. Such typically include anisotropic plasma etching through the conductive outer electrode material inwardly at least to the metal oxide which will be the programmable region of the memory cell. Further, usually subsequent plasma etching is conducted through the metal oxide to the lower electrode conductive material. Also, the metal oxide may be exposed to plasma-based post-etch cleans. Regardless, exposure of the metal oxide material to plasma etching can adversely affect the operation of the memory cell in that composition and/or structure of the metal oxide material may be modified in an unpredictable manner.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagrammatic top plan view of a semiconductor substrate fragment in process in accordance with an embodiment of the invention.

FIG. 2 is a cross sectional view of the FIG. 1 substrate fragment comprising a planar cross section taken through line 2-2 in FIG. 1.

FIG. 3 is a view of the FIG. 2 substrate fragment at a processing step subsequent to that shown by FIG. 2.

FIG. 4 is a view of the FIG. 3 substrate fragment at a processing step subsequent to that shown by FIG. 3.

FIG. 5 is a view of the FIG. 4 substrate fragment at a processing step subsequent to that shown by FIG. 4.

FIG. 6 is a diagrammatic top plan view of the FIG. 1 semiconductor substrate fragment at a processing step subsequent to that shown by FIG. 5.

FIG. 7 is a cross sectional view of the FIG. 6 substrate fragment comprising a planar cross section taken through line 7-7 in FIG. 6.

FIG. 8 is a cross sectional view of an alternate embodiment substrate fragment to that shown in FIG. 7.

FIG. 9 is a cross sectional view of an alternate embodiment substrate fragment to those shown in FIGS. 7 and 8.

FIG. 10 is a cross sectional view of an alternate embodiment substrate fragment to those shown in FIG. 7-9.

FIG. 11 is a diagrammatic isometric view of a semiconductor substrate fragment in process in accordance with an embodiment of the invention.

FIG. 12 is a view of the FIG. 11 substrate fragment at a processing step subsequent to that shown by FIG. 11.

FIG. 13 is a view of the FIG. 12 substrate fragment at a processing step subsequent to that shown by FIG. 12.

FIG. 14 is a view of the FIG. 13 substrate fragment at a processing step subsequent to that shown by FIG. 13.

FIG. 15 is a view of the FIG. 14 substrate fragment at a processing step subsequent to that shown by FIG. 14.

FIG. 16 is a view of the FIG. 15 substrate fragment at a processing step subsequent to that shown by FIG. 15.

FIG. 17 is a view of the FIG. 16 substrate fragment at a processing step subsequent to that shown by FIG. 16.

FIG. 18 is a diagrammatic isometric view of a semiconductor substrate fragment in process in accordance with an embodiment of the invention.

FIG. 19 is a view of the FIG. 18 substrate fragment at a processing step subsequent to that shown by FIG. 18.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

Example embodiments of forming a non-volatile resistive oxide memory cell and of forming a non-volatile resistive oxide memory array are initially described with reference to FIGS. 1-10. Referring initially to FIGS. 1 and 2, a substrate, for example a semiconductor substrate is indicated generally with reference numeral 10. In the context of this document, the term “semiconductor substrate” or “semiconductive substrate” is defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductive substrates described above. Substrate fragment 10 comprises material 12 over which a series of conductive lines 13, 14 and 15 has been fabricated. Multiple different materials and layers would likely be present at least below material 12, and may for example comprise bulk semiconductor processing, semiconductor-on-insulator processing, or other substrates in process and whether existing or yet-to-be developed. In one example, material 12 is insulative, for example doped and/or undoped silicon dioxide. Insulative material 12 is also shown as being received between conductive lines 13, 14 and 15. Conductive lines 13, 14 and 15 may be comprised of one or more conductive materials and/or layers, including conductively doped semiconductive material.

Portions of each of conductive lines 13, 14 and 15 will comprise a first conductive electrode of a memory cell which will be fabricated. A plurality of non-volatile resistive oxide memory cells may be fabricated within a memory array, thereby for example perhaps millions of such individual memory cells being fabricated at essentially the same time. Further, each of conductive lines 13, 14 and 15 may constitute a first conductive electrode of multiple different memory cells, as will be apparent in the continuing discussion. Conductive lines 13, 14 and 15 comprise an example of a plurality of one of conductive word lines or conductive bit lines which have been formed over a substrate. In other words, each of the depicted conductive lines 13, 14 and 15 will comprise conductive word lines or each of conductive lines 13, 14 and 15 will comprise conductive bit lines. In the depicted and but one example embodiment, the lines 13, 14 and 15 run in respective straight lines within the array, although other configurations are of course contemplated.

Referring to FIG. 3, a metal oxide-comprising material 18 has been formed over first conductive electrode 15, and accordingly over the one of conductive word lines 13, 14, and 15 or conductive bit lines 13, 14, and 15. Material 18 may or may not comprise an outermost planar surface. Material 18 may be homogenous or non-homogenous, and may comprise one or more different compositions and/or layers. Accordingly, material 18 may be deposited/formed in one or more steps. By ways of example only, material 18 might comprise multi-resistive state metal oxide-comprising material, further for example comprising two different layers or regions generally regarded as or understood to be active or passive regions, although not necessarily. Example active cell region compositions which comprise metal oxide and can be configured in multi-resistive states include one or a combination of Sr_(x)Ru_(y)O_(z), Ru_(x)O_(y), and In_(x)Sn_(y)O_(z). Other examples include MgO, Ta₂O₅, SrTiO₃, ZrO_(x) (perhaps doped with La), and CaMnO₃ (doped with one or more of Pr, La, Sr, or Sm). Example passive cell region compositions include one or a combination of Al₂O₃, TiO₂, and HfO₂. Regardless, multi-resistive state metal oxide-comprising material 28 might comprise additional metal oxide or other materials not comprising metal oxide. Example materials and constructions for a multi-resistive state region comprising one or more layers including a programmable metal oxide-comprising material are described and disclosed in U.S. Pat. Nos. 6,753,561; 7,149,108; 7,067,862; and 7,187,201, as well as in U.S. Patent Application Publication Nos. 2006/0171200 and 2007/0173019, the disclosures of which are hereby fully incorporated herein by reference for all purposes of this disclosure. Further as is conventional, multi-resistive state metal oxide-comprising materials encompass filament-type metal oxides, ferroelectric metal oxides and others, and whether existing or yet-to-be developed, as long as resistance of the metal oxide-comprising material can be selectively changed. Further, metal oxide-comprising material 18 might be configured to have its current leakage capabilities be selectively varied in addition to or instead of its resistive state.

Referring to FIG. 4, etch stop material 20 has been deposited over metal oxide-comprising material 18. In one embodiment and as shown, etch stop material is homogenous and in one embodiment is completely blanketly covering over metal oxide-comprising material 18. Regardless, etch stop material 20 will be used to provide an etch stopping function when etching a subsequently deposited conductive material, as will be described below. In one embodiment, etch stop material 20 comprises an inherently/always electrically conductive material, for example an inherently/always electrically conductive metal oxide. By ways of examples only, inherently/always electrically conductive materials include indium tin oxide, TiN, oxygen doped TiN, and RuO₂. Accordingly, etch stop material 20 may comprise one or more of such compositions.

In one embodiment, etch stop material 20 is of an electrically insulative composition yet is of an effective thinness in such instances to be electrically conductive through such composition. Composition of etch stop material 20 in such instances will determine maximum thickness of material 20 in a finished circuitry construction to enable electrical conduction through such composition. Example electrically insulative compositions for etch stop material 20 comprise at least one of silicon dioxide, silicon nitride, silicon oxynitride, silicon carbide, and titanium dioxide. In some embodiments, etch stop material 20 has a thickness no greater than 200 Angstroms in a finished circuitry construction incorporating the memory cell or cells being fabricated, and in one embodiment no greater than 100 Angstroms in such finished circuitry construction. In one embodiment, an example thickness range for etch stop material 20 in a finished circuitry construction incorporating such etch stop material is from 50 Angstroms to 200 Angstroms, although thicknesses less than 50 Angstroms are also of course contemplated.

Referring to FIG. 5, conductive material 22 has been deposited over etch stop material 20. Conductive material 22 may be homogenous or non-homogenous, and regardless be of the same or different composition from that of conductive material of first electrode 15.

Referring to FIGS. 6 and 7, a plurality of the other of conductive word lines 24, 25, 26 or conductive bit lines 24, 25, 26 has been formed from conductive material 22. An example technique for forming conductive lines 24, 25, and 26 comprises photolithographic patterning of an imageable material, such as photoresist, followed by develop and subsequent subtractive etch of material 22 to produce the FIGS. 6 and 7 construction. Portions of each of lines 24, 25, and 26 will comprise second conductive electrodes of the respective memory cells being fabricated. Regardless, the forming of the second conductive electrode 24, 25, and 26 of a respective memory cell comprises etching through conductive material 22 to stop etching action relative to etch stop material 20. Accordingly, etch stop material 20 provides an effective etch stopping function when etching through material 22 to form the depicted plurality of the other of conductive word lines 24, 25, 26 or conductive bit lines 24, 25, 26.

By way of example only, FIGS. 6 and 7 depict respective non-volatile resistive oxide memory cells 30 which comprise a portion of conductive line 15 which comprises a first conductive electrode of the respective memory cells, and a second conductive electrode comprising portions of one of the depicted conductive lines 24, 25, and 26. The respective memory cells 30 also comprise both metal oxide-comprising material 18 and etch stop material 20 which are received between the respective first and second conductive electrodes of the respective memory cells. Accordingly, etch stop material 20 comprises a part of the finished circuitry construction incorporating an individual memory cell. In the depicted and example but one embodiment, etch stop material 20 is completely blanketly covering between metal oxide-comprising material 18 and the overlying second conductive electrode in a finished circuitry construction incorporating the memory cell. In one embodiment wherein etch stop material 20 is of an electrically insulative composition, such material 20 is of an effective thinness between the respective first and second conductive electrodes to be electrically conductive through such composition when a multi-resistive state metal oxide-comprising material 18 is in a lowest resistive state, thereby for example for a binary memory cell enabling such cell to be switchable between “on” and “off” conditions.

In embodiments where etch stop material 20 is conductive, such is removed sufficiently (not shown in FIGS. 6 and 7) between/among memory cells 30 to preclude electrical shorting of different memory cells 30. In embodiments where etch stop material 20 is insulative, such may or may not need to be any of treated, removed partially, removed wholly, or not removed at all between/among memory cells 30 to preclude electrical shorting of different memory cells 30. Such may depend at least in part upon the dielectric properties of etch stop material 20 and/or spacing between adjacent memory cells 30. For example in the embodiment of FIGS. 6 and 7, composition of an insulative etch stop material 20 might be both (a) insufficiently resistive to enable conductivity between electrodes 22 and 15 when material 18 is in a lowest resistance state due in part to separation distance between electrodes 22 and 15 in a memory cell, and (b) sufficiently resistive between adjacent memory cells 30 due to greater separation distance therebetween as compared to the separation distance between electrodes 22 and 15 in a memory cell. Yet if condition (a) is satisfied and condition (b) is not, etch stop material 20 between memory cells 30 might be one or both of i) treated to increase resistivity thereof, or ii) thinned. Such might be desirable to minimize electrical interference between or among spaced memory cells 30, and further may be desirable even if both conditions (a) and (b) are satisfied. For example, segments of etch stop material 20 remaining between adjacent memory cells 30 might adversely or unpredictably impact programming voltage required to change states of material 18 in spaced memory cells 30. Thinning and/or treating to increase resistance of such material 20 between memory cells 30 might be used in such instances.

Regardless, different dielectric materials 20 can be deposited in one lower resistance state and treated after deposition to a second higher resistance state. For example, lower density of a given inherently/always dielectric material typically results in lower resistivity as compared to higher density of the same material. As one example, a low density silicon dioxide can be increased in density and resistance by treating with ozone with deionized water at elevated temperature. In another embodiment, etch stop material 20 can be removed to material 18 between memory cells 30 such that material 20 does not interconnect among individual memory cells 30.

In one embodiment, the act of etching through conductive material 22 to form the respective second conductive electrode portions of the memory cell stops on etch stop material 20 such that no detectable quantity of etch stop material 20 is etched during any of the etching of such conductive material 22. For example and by way of example only, FIG. 7 depicts a perfect selective etch of material 22 relative to etch stop material 20 such that none of etch stop material 20 is etched away after clearing conductive material 22 from between the depicted other of conductive word lines 24, 25, 26 or conductive bit lines 24, 25, 26.

Yet an alternate embodiment comprises etching through conductive material 22 whereby etch stop material 20 is only partially etched into upon complete etching through material 22 between conductive lines 24, 25, and 26, and accordingly still providing an etch stopping function during the etch of conductive material 22. Such partial etching into etch stop material 20 while etching conductive material 22 might, for example, etch less or more than half of thickness of etch stop material 20, or about half of thickness of etch stop material 20. For example and by way of examples only, FIG. 8 illustrates an alternate embodiment substrate fragment 10 a wherein etching of conductive material 22 has also etched partially into etch stop material 20 to less than half of the thickness of etch stop material 20. FIG. 9 illustrates an alternate embodiment substrate fragment 10 b wherein etching through conductive material 22 has etched partially into etch stop material 20 to more than half of the thickness etch stop material 20. Regardless, any etching of etch stop material 20 while etching conductive material 22 may or may not result in some lateral recess of material 22 relative to one or both of the respective first and second conductive electrodes, whereby the etch stop material may not be completely blanketly covering between the metal oxide-comprising material and the second conductive electrode in a finished circuitry construction incorporating the memory cell. Regardless, subsequently deposited insulative and wiring layers (not shown as not being material to the inventions disclosed herein) would likely be provided over each of the substrates of FIGS. 7, 8, and 9 in respective finished circuitry constructions.

In some embodiments, methods of forming a non-volatile resistive oxide memory cell and/or memory array are void of exposing any of metal oxide-comprising material 18 to any etching plasma, for example as may be desirable to overcome one or more problems identified in the Background section above. Alternately in some embodiments, metal oxide-comprising material 18 may be exposed to an etching plasma. Regardless, some embodiments of the invention also contemplate etching through etch stop material 20 laterally outward of the second conductive electrode to the metal oxide-comprising material after etching through the conductive material and using the etch stopping attribute or act relative to the etch stop material. For example, FIG. 10 illustrates an alternate embodiment substrate fragment 10 c which could result from subsequent processing of any of the substrate fragments 10, 10 a, or 10 b of FIGS. 7, 8, and 9, respectively. Substrate fragment 10 c in FIG. 10 has been processed to etch through etch stop material 20 laterally outward of each of the depicted second conductive electrodes 24, 25, and 26 to metal oxide-comprising material 18. Such subsequent etching of etch stop material 20 may or may not be conducted selectively relative to metal oxide-comprising material 18, and may or may not comprise wet, dry, and/or plasma etching.

In the above depicted and described example embodiments, programmable junctions or memory cells manifest where the respective word lines and bit lines cross one another. Further by way of example only and as shown in the above embodiments, the plurality of the other of conductive word lines 24, 25, 26 or conductive bit lines 24, 25, 26 run generally parallel an outer major surface of the substrate (as do the plurality of one of conductive word lines 13, 14, 15 or conductive bit lines 13, 14, 15), and are angled relative to the plurality of such one of word lines 13, 14, 15 or bit lines 13, 14, 15. The outermost surface of the respective substrates may or may not be planar at certain or any points during processing. Regardless, the above-described and depicted substrates at their respective largest or global scales can be considered as having some respective outer major surface that can be considered, on average, as defining some general horizontal plane relative to which the various layers and circuitry components are fabricated. Such outer major surface of the respective substrates may, of course, be comprised of more than one composition at different points in processing of the respective substrates. Further, the outer major surface of the respective substrates can be considered as averaging to be planar throughout fabrication, with such general plane rising and lowering as the circuitry is fabricated.

By ways of examples only, alternate exemplary embodiments of methods of forming a non-volatile resistive oxide memory cell and/or array are next described with reference to FIGS. 11-19. Referring initially to FIG. 11, a substrate fragment is indicated generally with reference numeral 40. Such comprises material 42 relative to which a series of conductive lines has been fabricated, for example lines 44 and 46. As above, multiple different materials and layers would likely be present at least below material 42 (as in accordance with material 12 in the above-described embodiments), and may for example comprise bulk semiconductor processing, semiconductor-on-insulator processing, or other substrates in process and whether existing or yet-to-be developed. In one example, material 42 is insulative, for example doped and/or undoped silicon dioxide. Insulative material 42 is also shown as being received between conductive lines 44 and 46. Conductive lines 44 and 46 may be comprised of one or more conductive materials and/or layers, including conductively doped semiconductive material.

Portions of each of conductive lines 44 and 46 will comprise a first conductive electrode of a respective memory cell which will be fabricated. As in the above-described embodiments, a plurality of non-volatile resistive oxide memory cells may be fabricated within a memory array, thereby for example perhaps millions of such individual memory cells being fabricated at essentially the same time. Further, each of conductive lines 44 and 46 may constitute a first conductive electrode of multiple different memory cells. Conductive lines 44 and 46 comprise an example of a plurality of one of conductive word lines or conductive bit lines which have been formed over a substrate. In other words, each of the depicted conductive lines 44 and 46 will comprise conductive word lines or each of conductive lines 44 and 46 will comprise conductive bit lines. In the depicted and but one example embodiment, lines 44 and 46 run in respective straight lines within the array, although other configurations are of course contemplated.

Metal oxide-comprising material 48 has been formed over the one of conductive word lines 44, 46 or conductive bit lines 44, 46. Example materials and constructions are as described above in the first-described embodiments with respect to material 18.

Etch stop material 50 has been deposited over metal oxide-comprising material 48. Example compositions and constructions are as described above in the first-described embodiments in connection with etch stop material 20. However, none or some of etch stop material 20 may remain in a finished circuitry construction of a non-volatile resistive oxide memory cell in the embodiments of FIGS. 11-19, as will be apparent from the continuing discussion.

Damascene template material 52 has been deposited over etch stop material 50. By ways of example only, example damascene template materials include at least one of amorphous carbon, transparent carbon, photoresist, silicon nitride, silicon dioxide (whether doped or undoped and including silicate glasses) and polysilicon (whether doped or undoped).

Referring to FIG. 12, a series of elongated trenches 60, 62 has been etched into damascene template material 52 to etch stop material 50 over the plurality of the one of word lines 44, 46 or bit lines 44, 46 to stop relative to etch stop material 50. In one embodiment and alternately considered, for example considered in the fabrication of a single non-volatile resistive oxide memory cell, either of trenches 60, 62 might be considered as an opening which has been etched through damascene template material 52 to etch stop material 50 over a first conductive electrode comprised of a portion of either of conductive lines 44, 46 to stop relative to etch stop material 50. Accordingly in the depicted embodiment, such an example opening comprises an elongated trench in the damascene template material which runs generally parallel an outer major surface of the substrate, and which are angled relative to the plurality of the one of word lines 44, 46 or bit lines 44, 46. Some of etch stop material 50 might also be etched into while still providing an etch stopping function.

Referring to FIG. 13, etching has been conducted through etch stop material 50 within the respective openings 60, 62 to metal oxide-comprising material 48. Any suitable wet or dry etching chemistry might be utilized. In one embodiment, such etching does not utilize any etching plasma such that the process is void of exposing metal oxide-comprising material 50 within the respective openings 60, 62 to any etching plasma, for example to overcome one or more of the problems identified in the Background section above. By way of example only where, for example, the etch stop material comprises silicon dioxide, a suitable dry non-plasma etching chemistry comprises use of NH₃ and HF vapors, and/or NF₃ radicals. Regardless, in one embodiment, ion implanting of a suitable substance might be conducted into etch stop material 50 within the respective opening 60, 62, or even before deposition of damascene template material 52, to facilitate ease of etching of etch stop material 50 from within the respective openings 60, 62. Regardless, in some embodiments, etching of etch stop material 50 within openings 60, 62 may or may not recess material 50 laterally beneath damascene template material 52. If such lateral recessing occurs and produces a less than desirable resultant outline, subsequent etching might be conducted at least of the sidewalls of damascene template material 52 to remove or reduce such recesses.

Referring to FIGS. 14 and 15, conductive material 64 has been deposited to within the respective opening 60, 62 over metal oxide-comprising material 48 and the respective first conductive electrodes 44, 46. FIGS. 14 and 15 depict an example embodiment whereby conductive material 64 has been deposited to overfill the respective openings/trenches 60, 62, and then polished back to at least an outermost surface of damascene template material 52. In the depicted example embodiment wherein a non-volatile resistive oxide memory array is also fabricated, a plurality of the other of conductive word lines 70, 72 or conductive bit lines 70, 72 has been formed from conductive material 64.

Some or all of damascene template material may remain as part of the finished circuitry construction where such is of a desired insulative material. Alternately and by way of example only and referring to FIG. 16, all remaining of damascene template material 52 (not shown) has been removed from the substrate.

Some, none, or all of remaining etch stop material 50 may be removed from the substrate, with FIG. 17 showing an example embodiment wherein all such remaining etch stop material 50 (not shown) has been removed from the substrate. Regardless, metal oxide-comprising material 48 between the one of word lines 44, 46 or bit lines 44, 46 and the other of word lines 70, 72 or bit lines 70, 72 form individually programmable junctions where the word lines and bit lines cross one another, thereby forming the depicted example individual non-volatile resistive oxide memory cells 75.

By ways of example only, the above-described embodiments depict non-volatile resistive oxide memory cells and memory arrays where word lines and bit lines cross one another without isolation patterning of the metal oxide-comprising material and without a conductive projection extending from one or both of the word lines or bit lines for each memory cell. However of course, embodiments of the invention encompass incorporating these or other features in a memory cell or an array of memory cells. For example, the metal oxide-comprising material might be patterned relative to one or a plurality of memory cells, and/or one or more conductive projections might be provided relative to the respective word lines and/or bit lines.

By way of example only, FIGS. 18 and 19 depict an alternate exemplary embodiment with respect to a substrate fragment 40 a. Like numerals from the FIGS. 11-17 embodiment have been utilized where appropriate, with differences being indicated with the suffix “a” or with different numerals. FIG. 18 corresponds in processing sequence to FIG. 11 of the substrate fragment embodiment of FIG. 11, yet wherein a plurality of respective conductive projections 80 extend upwardly from word lines 44, 46 or bit lines 44, 46. Accordingly in one example embodiment, such comprise first conductive electrodes of respective non-volatile resistive oxide memory cells. Such conductive projection extending upwardly from a conductive line 44, 46 may be of the same or different composition from that of the conductive line. By way of example only, conductive lines 44, 46 and respective projections 80 are depicted as being of the same composition, and may comprise one or more conductive materials including conductively doped semiconductive material. An example manner of fabricating conductive lines 44, 46 to include projections 80 includes initial deposition of one or more conductive materials to a thickness at or greater than the thickness of a conductive projection including that of the underlying conductive line. The outline of the conductive lines can then be patterned. This can be followed by cross patterning of the conductive projections using a timed etch into the conductive material from which such projections and lines are formed. Other manners of fabrication might be used.

Regardless, FIG. 19 depicts an analogous construction to that of FIG. 17 but additionally incorporating projections 80 to thereby form individual non-volatile resistive oxide memory cells 75 a. Nevertheless and regardless, such still defines or forms a non-volatile resistive oxide memory array comprising metal oxide-comprising material received between the one of the word lines or bit lines and the other of the word lines or bit lines to form individually programmable junctions where the word lines and bit lines cross one another. Of course alternately or in addition thereto, downward projections might be provided from the overlying conductive lines 70, 72. Further, either or both of such projection concepts and/or isolation patterning of metal oxide-comprising material might be incorporated in any of the above-described FIGS. 1-10 embodiments.

In compliance with the statute, the subject matter disclosed herein has been described in language more or less specific as to structural and methodical features. It is to be understood, however, that the claims are not limited to the specific features shown and described, since the means herein disclosed comprise example embodiments. The claims are thus to be afforded full scope as literally worded, and to be appropriately interpreted in accordance with the doctrine of equivalents. 

1. A method of forming a non-volatile resistive oxide memory cell, comprising: forming a first conductive electrode of the memory cell as part of a substrate; forming metal oxide-comprising material over the first conductive electrode; depositing etch stop material over the metal oxide-comprising material; depositing damascene template material over the etch stop material; etching an opening through the damascene template material to the etch stop material over the first electrode to stop relative to the etch stop material; after etching the opening through the damascene template material to the etch stop material over the first electrode to stop relative to the etch stop material, etching through the etch stop material within the opening to the metal oxide-comprising material; after etching through the etch stop material within the opening to the metal oxide-comprising material, depositing conductive material to within the opening over the metal oxide-comprising material and the first conductive electrode and forming a second conductive electrode of the memory cell from the conductive material.
 2. The method of claim 1 comprising after etching the opening through the damascene template material to the etch stop material over the first electrode to stop relative to the etch stop material and before etching through the etch stop material within the opening to the metal oxide-comprising material, ion implanting a substance into the etch stop material within the opening.
 3. The method of claim 1 being void of exposing said metal oxide-comprising material within the opening to any etching plasma.
 4. The method of claim 1 being void of exposing said metal oxide-comprising material to any etching plasma.
 5. The method of claim 1 wherein the opening comprises an elongated trench in the damascene template material that runs generally parallel an outer major surface of the substrate.
 6. The method of claim 1 wherein the etch stop material comprises at least one of silicon dioxide, silicon nitride, silicon oxynitride, silicon carbide, and titanium dioxide.
 7. The method of claim 1 wherein the etch stop material comprises silicon dioxide, and the etching through the etch stop material comprises using at least one of a) NH₃ and HF vapors, and b) NF₃ radicals.
 8. The method of claim 1 comprising after depositing the conductive material, removing all remaining of said damascene template material from the substrate.
 9. The method of claim 1 wherein the damascene template material comprises at least one of transparent carbon, photoresist, silicon nitride, silicon dioxide, and polysilicon.
 10. The method of claim 1 comprising after depositing the conductive material and before removing all remaining of said damascene template material, polishing the conductive material back to at least an outermost surface of the damascene template material.
 11. The method of claim 1 wherein the metal oxide-comprising material comprises multi-resistive state metal oxide-comprising material.
 12. A method of forming a non-volatile resistive oxide memory array, comprising: forming a plurality of one of conductive word lines or conductive bit lines over a substrate; forming multi-resistive state metal oxide-comprising material over the one of conductive word lines or conductive bit lines; depositing etch stop material over the multi-resistive state metal oxide-comprising material; depositing damascene template material over the etch stop material; etching a series of elongated trenches into the damascene template material to the etch stop material over the plurality of said one of word lines or bit lines to stop relative to the etch stop material, the trenches running generally parallel an outer major surface of the substrate, the trenches being angled relative to the plurality of said one of word lines or bit lines; after etching said elongated trenches to stop relative to the etch stop material, etching through the etch stop material within the elongated trenches to the multi-resistive state metal oxide-comprising material; after etching through the etch stop material within the elongated trenches to the multi-resistive state metal oxide-comprising material, depositing conductive material to within the elongated trenches over the multi-resistive state metal oxide-comprising material and the one of conductive word lines or conductive bit lines, and forming a plurality of the other of conductive word lines or conductive bit lines from the conductive material; and providing said multi-resistive state metal oxide-comprising material between said one of word lines or bit lines and said other of word lines or bit lines to form individually programmable junctions where the word lines and bit lines cross one another.
 13. The method of claim 12 comprising after depositing the conductive material, removing all remaining of said damascene template material from the substrate.
 14. The method of claim 12 wherein the metal oxide of the metal oxide comprising material comprises one or more member selected from the group consisting of Sr_(x)Ru_(y)O_(z), RuO_(y), In_(x)Sn_(y)O_(z), and CaMnO₃.
 15. A method of forming a non-volatile resistive oxide memory cell, comprising: forming a first conductive electrode of the memory cell as part of a substrate; forming metal oxide-comprising material over the first conductive electrode; depositing etch stop material over the metal oxide-comprising material; depositing damascene template material over the etch stop material; etching an opening through the damascene template material to the etch stop material over the first electrode to stop relative to the etch stop material; etching through the etch stop material within the opening to the metal oxide-comprising material while retaining laterally extending regions of the etch stop material, at least a portion of the laterally extending regions being retained in a final memory cell structure; depositing conductive material to within the opening over the metal oxide-comprising material.
 16. The method of claim 15 wherein the metal oxide-comprising material is formed in direct physical contact with the first conductive electrode.
 17. The method of claim 15 wherein the metal oxide of the metal oxide comprising material comprises one or more member selected from the group consisting of Sr_(x)Ru_(y)O_(z), RuO_(y), In_(x)Sn_(y)O_(z), and CaMnO₃.
 18. The method of claim 15 wherein the etch stop is deposited in direct physical contact with the metal oxide-comprising material.
 19. The method of claim 15 wherein the first conductive electrode comprises doped semiconductive material.
 20. The method of claim 15 further comprising modifying the laterally extending regions of etch stop, the modifying comprising at least one of treating the etch stop to increase resistivity and removal of part of a thickness of the extending portions of etch stop. 